Integrated circuit design involves timing closure, which is the process by which designs can be modified to meet timing requirements. A typical design process for an Application Specific Integrated Circuit (ASIC) oftentimes includes logic design, floor planning, placement, layout, clock tree balancing, fixing setup times, and fixing hold times. The combination of clock tree balancing, fixing of setup times, and fixing of hold times is commonly referred to as timing closure. For a typical ASIC that includes digital components, timing closure can be effectuated with a high degree of accuracy since the behavior of clocks, storage elements (e.g., flip flops, latches, memories, . . . ), etc. can be accurately simulated.
Meanwhile, timing closure associated with mixed signal circuits is typically more difficult and less accurate as compared with digital circuits. Mixed signal design with digital component(s) and analog component(s) (e.g., image sensors) commonly cannot be simulated accurately to provide satisfactory timing closure. For example, a timing model can be yielded for digital logic (e.g., prior to fabrication), whereas an analog portion of a mixed signal ASIC typically cannot be characterized until the ASIC is fabricated and tested. Automation of circuit design associated with analog or mixed signal integrated circuits tends to be limited in comparison to digital circuit design. Further, testing functional operation of mixed signal integrated circuits typically is complex, expensive, and time consuming.
Recent technological advances have led to CMOS sensor imagers being leveraged by cameras, video systems, and the like. CMOS sensor imagers can include an integrated circuit with an array of pixel sensors, each of which can comprise a photodetector. Moreover, a CMOS sensor imager can be incorporated into a system-on-a-chip (SOC). As such, the SOC can integrate various components (e.g., analog, digital, . . . ) associated with imaging into a common integrated circuit. For instance, the SOC can include a microprocessor, microcontroller, or digital signal processor (DSP) core, memory, analog interfaces (e.g., analog to digital converters, digital to analog converters), and so forth. However, timing closure associated with such mixed signal SOC's typically is costly, difficult, and time consuming at best. Further, conventional techniques that address timing closure for mixed signal SOC's oftentimes inefficiently overcompensate or under compensate for timing lags within the SOC's.